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QS5930T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FEATURES:
* * * * * * * * * * * * * 5V operation Q/2 output, 5 Q outputs Useful for Pentium, PowerPC, and PCI systems Internal loop filter RC network Low noise TTL level outputs <250ps rising edge output skew Balanced drive outputs 24mA PLL bypass feature for low frequency testing Internal VCO/2 option for wider frequency range Outputs tri-state and reset while OE/RST is low ESD > 2000V Latch up > -300mA Available in QSOP package
QS5930T
DESCRIPTION
The QS5930T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to a reference clock input. Six outputs are available: Q0-Q4, Q/2. Careful layout and design ensure < 250ps skew between the Q0-Q4, and Q/2 outputs. The QS5930T includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The QS5930T is designed for use in cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. In the QSOP package, the QS5930T clock driver represents the best value in small form factor, high-performance clock management products. For more information on PLL clock driver products, see Application Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK PLL_EN FREQ _SEL
SYNC O E/RST
PH ASE DETECTO R LOO P FILTER
0
1
VCO
1
/2
0
R
D
R
D
R
D
R
D
R
D
R
D
Q
Q
Q
Q
Q
Q
Q
Q /2
Q4
Q3
Q2
Q1
Q0
INDUSTRIAL TEMPERATURE RANGE
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c 2000 Integrated Device Technology, Inc.
SEPTEMBER 2000
DSC-5849
QS5930T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Symbol Rating AVDD,VDD Supply Voltage to Ground Max. -0.5 to +7 -0.5 to +7 -3 DC Input Voltage VIN AC Input Voltage (for pulse width 20ns) TSTG Maximum Power Dissipation (TA = 85C) Storage Temperature Range
(1)
Unit V V V W C
GND OE/RST FEEDBACK AVDD VDD AGND SYNC FREQ_SEL GND Q0
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Q4 Q/2 GND Q3 VDD Q2 GND PLL_EN GND Q1
1 -65 to +150
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = 25 C, f = 1MHz, VIN = 0V)
Pins CIN COUT Typ. 3 7 Max. 4 9 Unit pF pF
QSOP TOP VIEW
PIN DESCRIPTION
Pin Name SYNC FREQ_SEL FEEDBACK Q0 -Q4 Q/2 OE/RST PLL_EN VDD AVDD GND AGND I/O I I I O O I I -- -- -- -- Reference clock input VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. HIGH is for higher frequencies, LOW is for lower frequencies. PLL feedback input which is connected to either a Q or a Q/2 output. External feedback provides flexibility for different output frequency relationships. See the Frequency Selection Table for more information. Clock outputs Clock output. Matched in phase, but frequency is half the Q frequency. Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled. PLL enable. Enables and disables the PLL. Allows the SYNC input to be single-stepped for system debug. Power supply for output buffers. Power supply for phase lock loop and other internal circuitries. Ground supply for output buffers. Ground supply for phase lock loop and other internal circuitries. Description
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: TA = -40C to +85C, AVDD/VDD = 5V 10%
Symbol FMAX_Q FMAX_Q/2 FMIN_Q FMIN_Q/2 Description Max Frequency, Q0 - Q4, Max Frequency, Q/2 Min Frequency, Q0 - Q4 Min Frequency, Q/2 - 50 50 25 28 14 - 66 66 33 28 14 Units MHz MHz MHz MHz
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QS5930T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
FREQUENCY SELECTION TABLE
FREQ_SEL HIGH HIGH LOW LOW Output Used for Feedback Q/2 Q0 -Q4 Q/2 Q0 -Q4 SYNC (MHz) (allowable range) (1) Min. 14 28 7 14 Max FMAX _Q/2 FMAX _Q FMAX _Q/2 /2 FMAX _Q /2 Output Frequency Relationships Q/2 Q0 - Q4 SYNC SYNC / 2 SYNC SYNC / 2 SYNC X 2 SYNC SYNC X 2 SYNC
NOTE: 1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 28MHz to FMAX_Q x2. Operation with Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, AVDD/VDD = 5V 5%
Symbol VIH VIL VOH VOL IOZ IIN Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Output Leakage Current Input Leakage Current Conditions Guaranteed Logic HIGH Level Guaranteed Logic LOW Level IOH = -24mA IOH = -100A VDD = Min., IOL = 24mA VDD = Min., IOL = 100A VOUT = VDD or GND, VDD = Max., Outputs Disabled AVDD = Max., VIN = AVDD or GND Min. 2 -- 2.4 3 -- -- -- -- Typ. -- -- -- -- -- -- -- -- Max. -- 0.8 -- -- 0.55 0.2 5 5 Unit V V V V V V A A
POWER SUPPLY CHARACTERISTICS
Symbol IDDQ IDD IDDD Parameter Quiescent Power Supply Current Power Supply Current per Input HIGH Dynamic Power Supply Current Test Conditions VDD = Max., OE/RST = LOW, SYNC = LOW, All outputs unloaded VDD = Max., VIN = 3V VDD = Max., CL = 0pF Typ. -- 1 0.2 Max. 1 30 0.3 Unit mA A mA/MHz
INPUT TIMING REQUIREMENTS
Symbol tR, tF FI tPWC DH Description (1) Maximum input rise and fall times, 0.8V to 2V Input Clock Frequency, SYNC Duty Cycle, SYNC (2)
(1)
Min. -- 7 2 25
Max. 3 FMAX _Q -- 75
Unit ns MHz ns %
Input clock pulse, HIGH or LOW (2)
NOTES: 1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and FREQ_SEL combinations. 2. Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies
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QS5930T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol tSKR tSKF tPW tJ tPD tPZH tPZL tPHZ tPLZ tR, tF Parameter (1) Output Skew Between Rising Edges, Q0-Q4 (and Q/2) (2) Output Skew Between Falling Edges, Q0-Q4 (and Q/2) (2) Pulse Width, Q0-Q4, Q/2 outputs, 80MHz Cycle-to-Cycle Jitter, FI > 33MHz
( 4)
Min. -- -- TCY/2 - 0.5 -- - 100 0 0 0.4
Max. 250 350 TCY/2 + 0.5 250 +400 7 6 1.5
Unit ps ps ns ns ps ns ns ns
SYNC Input to Feedback Delay ( 5) Output Enable Time, OE/RST LOW to HIGH ( 3) Output Disable Time, OE/RST HIGH to LOW ( 3) Output Rise/Fall Times, 0.8V to 2V
NOTES: 1. See Test Loads and Waveforms for test load and termination. 2. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). 3. Measured in open loop mode PLL_EN = 0. 4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies. 5. tPD measured at device inputs at 1.5V, Q output at 28MHz.
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QS5930T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
AC TEST LOADS AND WAVEFORMS
VDD
300 7.0V OUTPUT 160
OUTPUT 300 68 28pF
30pF
TEST CIRCUIT 1
TEST CIRCUIT 2
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5930T provides for replication of incoming SYNC clock signals. Any manipulation of that signal, such as frequency multiplying, is performed by digital logic following the PLL (see the block diagram). The key advantage of the PLL circuit is to provide an effective zero propagation delay between the output and input signals. In fact, adding delay circuits in the feedback path, `propagation delay' can even be negative! A simplified schematic of the QS5930T PLL circuit is shown below:
SIMPLIFIED DIAGRAM OF QS5930T FEEDBACK
Q
Q /2
INPU T PHASE DETECTO R
VCO/2
/2
The phase difference between the output and the input frequencies feeds the VCO which drives the outputs. Whichever output is fed back, it will stabilize at the same frequency as the input. Hence, this is a true negative feedback closed loop system. In most applications, the output will optimally have zero phase shift with respect to the input. In fact, the internal loop filter on the QS5930T typically provides within 150ps of phase shift between input and output.
If the user wishes to vary the phase difference (typically to compensate for backplane delays), this is most easily accomplished by adding delay circuits to the feedback path. The respective output used for feedback will be advanced by the amount of delay in the feedback path. All other outputs will retain their proper relationships to that output.
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QS5930T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
QS XXXX Device Type XX Speed X Package X Process
Blank
Industrial (-40C to +85C)
Q
Quarter Size Outline Package
-50T -66T
50MHz. max. frequency 66MHz. max. frequency
5930
Low Skew CMOS PLL Clock Driver with Integrated Loop Filter
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for Tech Support: logichelp@idt.com (408) 654-6459
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